Loop Filter Design for Phase-Locked Loops with Guaranteed Lock-In Range

Lock-in range is one of the key parameters which govern the dynamic performance of a phaselocked loop (PLL). For low-order PLLs, coarse formulas can be derived under certain assumptions and approximation for designing loop filters to achieve the performance requirement. However, it is difficult, if not impossible, to establish such relations for high-order PLLs. In this paper, we propose a new loop filter design which, in addition to satisfying the prescribed lock-in range specification, achieves several other performance requirements as well, such as small noise bandwidth and good transient response (small settling time, small overshoot). The proposed method is applicable to PLLs of any order.